How To Change Instruction Format Based On No Of Registers

EECS 31/CSE 31/ICS 151 Homework viii Questions with Solutions

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Trouble 1

Question

(Instruction formats) Write a sequence of instructions that volition compute the value of y = xii + 2x + 3 for a given 10 using

1. 3-address instructions
2. two-accost instructions
3. ane-address instructions

Solution

1. iii-address instructions

                                 Mult z, x, x Mult y, 2, x  Add together y, y, z Add y, y, iii                          

2. two-accost instructions

                                 Move z, x Mult z, x Movement y, three Add together y, z Move z, x Mult z, 2 Add y, z                          

3. ane-accost instructions

                                 Move x Mult x Store z Motility x Mult two Add z Add 3 Shop y                          

Trouble ii

Question

(Addressing modes) Write procedures for reading from and writing to a FIFO queue, using a two-address format, in comjunction with:

1. indirect addressing
2. relative addressing

Solution

1.                               Reading:                Loadindirect                R3, R1          Inc R1                Writing:                Shopindirect                R2, Data          Inc R2                          

2. if we have a fixed base annals chosen BR:

                                 Reading:                Move temp, BR          Movement BR, R1          Loadrel                R4, showtime          Inc R1          Move BR, temp                Writing:                Move temp, BR          Move BR, R2          Storerel                beginning, Data          Inc R2          Motility BR, temp                          

Trouble iii

Question

(Addressing modes) Write a sequence of instructions that volition compute aixi where A = [a1, a2, ..., a100] and X = [x1, x2, ..., x100] represent arrays that are stored in the main retentiveness. Apply two-address instructions, in conjunction with:

1. direct addressing
2. relative addressing
3. indexed addressing with an machine-increment mode

Solution

1. Direct addressing:

                                 Move Sum, 0 Load Temp1, chiliad Load Temp2, 2000 Mult Temp1, Temp2 Add Sum, Temp1 ... Load Temp1, 1099 Load Temp2, 2099 Mult Temp1, Temp2 Add Sum, Temp1                          

2. relative addressing

                                 Move Sum, 0 Loadrel                Temp1, 0 Loadrel                Temp2, 100 Mult Temp1, Temp2 Add Sum, Temp1 ... Loadrel                Temp1, 99 Loadrel                Temp2, 199 Mult Temp1, Temp2 Add Sum, Temp1                          

3. indexed addressing with an auto-increment manner

                                 Move Sum, 0     Motion IR, 0 L1: Loadalphabetize                Temp1, 1000     Loadindex                Temp2, 2000     Mult Temp1, Temp2     Add Sum, Temp1     Cmp IR, 100     Bne L1                          

Problem 4

Question

(Instruction gear up) Add a dedicated base register ( BR ) to the 16-flake processor shown in Figure 9.9, then show the changes this requires in the instruction gear up and the processor schematic.

Solution

Add one instruction to load the base:

                      Lbase            Address : BR <-- Address                  

Change relative addressing:

                      Lrel            Dest, Base : RF[Dest] <-- Mem[BR + Offset]     Due southrel            Srcl, Base : Mem[BR + Starting time] <-- RF[Srcl]                  

The processor would need to be modified in the following fashion:

Trouble 5

Question

(Reduced instruction set) Using the education set presented in Effigy nine.11, suggest the changes that enable it so to adapt a register file with:

1. 16 registers
2. 32 registers
3. 64 registers
4. 256 registers

Solution

1. (a, b) Four bits are required to address 16 registers, and five bits are needed to address 32 registers. The simplest change to the didactics set would exist to reduce the size of the constant and kickoff fields by three $.25 to increase the bits used in the annals fields.
2. (c, d) For larger register files, simply reducing the get-go and constant fields will non be enough. Register instructions tin can altered by either removing the constant field or by assuming that i of the Src fields too acts as the Dest frees upwards bits.
3. Retentivity instructions to load and store relative to some address can be changed through the inclusion of a base register and removal of the Src2 field.
4. The branching instruction can be divided into two instructions, a comparison education and a branch teaching based upon a status register.

Trouble half dozen

Question

(IS flowchart) Develop an IS flowchart for the reduced instruction set presented in Effigy 9.eleven.

Solution

Problem vii

Question

(Branch prediction) Write a program that will compute accented value for the RISC processor shown in Effigy 9.12. Develop a timing diagram for this processor,

1. without branch prediction
2. with branch prediction

Solution

1. To realize this algorithm using our RISC instructions on the processor without branch prediction, we could program it equally follows:

   Address	Instruction
   100	Bgeq a, 0, +ix
   101	N o - op
   102	N o - op
   103	Northward o - op
   104	sub val, 0, a
   105	jump + 5
   106	N o - op
   107	N o - op
   108	N o - op
   109	Due north o - op
   110	...

   Timing diagram when branch is not taken ( a < 0 )

   

   Timing diagram when branch is taken ( a >= 0)

   

2. The program would change slightly when tuned for the processor with co-operative prediction

   Address	Teaching
   100	Bgeq a, 0, +3
   101	sub val, 0, a
   102	jump + ii
   103	mov val, a
   104	...

   Timing diagram when branch is not taken ( a < 0 )

   

   Timing diagram when branch is taken ( a >= 0 )

   

How To Change Instruction Format Based On No Of Registers,

Source: http://www.cecs.uci.edu/~gajski/eecs31/homeworks/hw8_solutions.html

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