What Is A Priority Register Verilog

Improperly coded Verilog case statements can frequently crusade unintended synthesis optimizations or unintended latches. These issues, if not defenseless in pre-silicon simulations or gate level simulations, can easily lead to a non-functional chip. The new SystemVerilog unique and priority keywords are designed to accost these coding traps. In this article, we will take a closer wait at how to use these new SystemVerilog keywords in RTL coding. The reader is assumed to have cognition of how Verilog example statements work. Those who are not familiar tin refer to my previous mail "Verilog twins: instance, casez, casex. Which Should I Utilise?"

The SystemVerilog unique and priority modifiers are placed before an if, case, casez, casex statement, like this:

unique if (expression)   statements else   statements  priority case (case_expression)   case_item_1: case_expression_1   case_item_2: case_expression_2 endcase

With the if…else statement, the SystemVerilog unique or priority keyword is placed only earlier the first if, but affects all subsequent else if and else statements.

SystemVerilog Unique Keyword

The unique keyword tells all software tools that support SystemVerilog, including those for simulation, synthesis, lint-checking, formal verification, that each selection item in a serial of decisions is unique from any other selection item in that series, and that all legal cases take been listed. In other words, each item is mutually exclusive, and the if…else or instance statement specifies all valid selection items.

It is easier to illustrate the effects of SystemVerilog unique using a case argument. unique case causes a simulator to add run-time checks that will report a warning if whatsoever of the following weather condition are true:

1. More than one case item matches the example expression
2. No case item matches the case expression, and there is no default case

To illustrate how SystemVerilog unique affects simulation of instance statements, let's look at a wildcard casez statement:

always @(irq) begin   {int2, int1, int0} = 3'b000;   unique casez (irq)     three'b1?? : int2 = 1'b1;     three'b?1? : int1 = ane'b1;     three'b??one : int0 = 1'b1;   endcase terminate

You may recognize that this lawmaking resembles the priority decoder example from my previous post "Verilog twins: case, casez, casex. Which Should I Use?" However, by adding the SystemVerilog unique keyword, the behaviour is at present completely different.

Firstly, by calculation the SystemVerilog unique keyword, the designer asserts that only one instance detail can match at a time. If more than than 1 flake of irq is fix in simulation, the simulator will generate a warning, flagging that the assumption of irq being one-hot has been violated. Secondly, to synthesis tools, the unique keyword tells the tool that all valid example items accept been specified, and can be evaluated in parallel. Synthesis is free to optimize the example items that are not listed.

Read the 2nd point once more, information technology is paramount! In a unique case argument (without a default example), outputs afterward synthesis from any unlisted case item is indeterminate. In simulation you may run into a deterministic behaviour, possibly fifty-fifty an output that looks right (along with an easy-to-miss warning), simply that may not match what you see in silicon. I have personally seen a chip that did not work because of this coding error.

Back to the instance, because of the unique keyword, synthesis volition remove the priority logic. Thus, this code instance is actually a decoder with no priority logic. Eliminating unnecessary priority logic typically results in smaller and faster logic, but only if information technology is indeed the designer'southward intention.

The SystemVerilog unique keyword can be applied similarly to an if…else statement to convey the same uniqueness properties. For a unique if argument, a simulator will generate a run-time warning if any of the following is imitation:

1. If two or more than of the if weather are true at the aforementioned time
2. If all of the if weather condition (including else if) are false, and there is no terminal else co-operative

SystemVerilog 2012 adds the keyword unique0 which, when used with a example or if argument, generates a warning merely for the first status above.

SystemVerilog Priority Keyword

The priority keyword instructs all tools that back up SystemVerilog that each selection item in a series of decisions must be evaluated in the order in which they are listed, and all legal cases take been listed. A synthesis tool is free to optimize the logic assuming that all other unlisted conditions are don't cares. If the priority case argument includes a case default argument, however, then the event of the priority keyword is disabled because the instance statement has then listed all possible conditions. In other words, the example statement is total.

Since the designer asserts that all conditions take been listed, a priority case will crusade simulators to add together run-time checks that volition report a alert for the following status:

1. If the case expression does not match any of the example item expressions, and there is no default example

A priority if volition cause simulators to report a warning if all of the if…if else conditions are false, and there is no final else branch. An else co-operative volition disable the issue of the priority if.

When to Use Them

SystemVerilog unique and priority should be used especially in instance statements that infer priority or non-priority logic. Using these keywords aid convey pattern intent, guide synthesis tools to the correct result, and adds simulation and formal verification assertions that check for violation of design assumptions. One suggestion from "full_case parallel_case", the Evil Twins of Verilog Synthesis is to code intentional priority encoders using if…else if statements rather than case statements, as information technology is easier for the typical engineer to recognize a priority encoder coded that mode.

SystemVerilog unique and priority exercise non guarantee the removal of unwanted latches. Any example statement that makes assignments to more than 1 output in each example item argument can even so generate latches if one or more output assignments are missing from other case detail statements. One of the easiest means to avoid these unwanted latches is past making a default assignment to the outputs before the case statement.

The unique and priority keywords should not exist blindly added to any instance and if statements either. Beneath is an example where the priority keyword will cause a design to break. The hardware that is intended is a decoder with enable en. When en=0, the decoder should output 4'b0000 on y.

logic [3:0] y; logic [one:0] a; logic       en;  always_comb begin   y = '0;   priority case ({en,a})     3'b100: y[a] = 1'b1;     3'b101: y[a] = 1'b1;     3'b110: y[a] = 1'b1;     3'b111: y[a] = 1'b1;   endcase stop

The logic will synthesize to something similar this:

Here the priority keyword indicates that all unlisted case items are don't cares, and can be optimized. As a result, the synthesis tool will simply optimize away en, which results in a different hardware than what was intended. A simulator will study a warning whenever en=0, which should raise an alarm warning that something is wrong. The unique keyword volition have the aforementioned effect here.

Decision

SystemVerilog unique and priority assistance avert bugs from incorrectly coded case and if…else statements. They are part of the SystemVerilog linguistic communication which ways all tools that support SystemVerilog, including those for simulation, lint-checking, formal verification, synthesis, all take to implement the same specification of these keywords. Using these keywords help convey design intent, guide synthesis tools to the correct effect, and adds simulation and formal verification checks for violation of design assumption.

In this mail service I have purposely tried to avert discussing the Verilog pragmas full_case and parallel_case to write a more stand-alone discussion of the SystemVerilog unique and priority keywords. Those who are interested in the historical development of these keywords from Verilog full_case and parallel_case can refer to "full_case parallel_case", the Evil Twins of Verilog Synthesis.

Do you have other experiences or examples of when to use or non utilize unique and priority? Leave a annotate below!

References

• "full_case parallel_case", the Evil Twins of Verilog Synthesis
• SystemVerilog Saves the Day—the Evil Twins are Defeated! "unique" and "priority" are the new Heroes
• SystemVerilog's priority & unique – A Solution to Verilog's "full_case" & "parallel_case" Evil Twins!

Quiz and Sample Source Code

Now it's time for a quiz! How will each of the post-obit variations of case statement behave when the example expression

1. matches ane of the non-default instance items
2. does not lucifer whatever not-default case item
3. contains all X'due south (e.g. if the signal comes from an uninitialized memory)
4. contains all Z's (e.g. if the signal is unconnected)
5. contains a unmarried bit X
6. contains a single bit Z?

Instance statement variations:

1. Evidently instance statement
2. Manifestly case with default case
3. Casez
4. Casez with default example
5. Casex
6. Casex with default case
7. Unique case
8. Unique case with default case
9. Unique casez
10. Unique casex

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Jason has 10 years' experience in the semiconductor manufacture, designing and verifying Solid State Drive controller SoC. His areas of workinclude microarchitecture and RTL design, dynamic and formal verification using UVM and Cadency JasperGold, and full-fleck low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.

Source: https://www.verilogpro.com/systemverilog-unique-priority/

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